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| July 2000 ML2652/ML2653 10Base-T Physical Interface Chip GENERAL DESCRIPTION The ML2652, 10BASE-T Physical Interface Chip, is a complete physical interface for twisted pair and AUI Ethernet applications. It combines a 10BASE-T MAU, Manchester Encoder/Decoder, and Twisted Pair Interface filters in one monolithic IC. A complete DTE interface for twisted pair Ethernet can be implemented by combining the ML2652, an Ethernet controller, and transformers. The ML2652 can automatically select between an AUI and twisted pair interface based on Link Pulses. Six LED outputs provide complete status at the physical link. Link pulse testing can be enabled or disabled through the LTP LED Pin. The unique transmitter design uses a waveform generator and low pass filter to meet the 10BASE-T transmitter requirements without the need for an external filter. The differential current driven output reduces common mode which in turn results in very low EMI and RFI noise. The ML2652 and ML2653 (28 pin version) are implemented in a low power double polysilicon CMOS technology. The ML2653 does not include the AUI interface. FEATURES s s s s s s s s s s Complete physical interface solution Conforms to IEEE 802.3i-1990 (10Base-T) On-chip transmit and receive filters Automatic AUI/Twisted Pair selection (ML2652 only) Power down mode Pin selectable controller interface-(CS0 - CS2) Intel 82586, 82596 NSC DP8390 Seeq 8003, 8005 AMD 7990 Automatic polarity correction Pin selectable receive squelch levels Status pins for: link detect, receive & transmit activity, collision, jabber, AUI selection Single supply 5V 5% ML2652 BLOCK DIAGRAM CS0 CS1 CS2 FD VCC VCC GND TxC TxE TxD DATA MANCHESTER ENCODER ENABLE COL LPBK RxC RxE RxD CLK ENABLE CONTROLLER INTERFACE COLLISION GND JABDIS JABBER DETECT LINK PULSE XMT WAVEFORM GEN & LPF COLLISION DETECT RECEIVE LPF RECEIVER RSL DO+ DO- AUI CI+ CI- DI+ DI- CURRENT DRIVEN XMT OUTPUT DRIVER RTX Tx+ Tx- Rx+ Rx- DATA MANCHESTER DECODER OSC LEDS RPOL AUISEL XMT CLS RCV LTP JAB AUI/TP 1 ML2652/ML2653 PIN CONNECTIONS ML2653 28-Pin PLCC (Q28) GND GND TxD RTX TxC Tx+ TxE ML2652 44-Pin PLCC (Q44) JABDIS GND GND TxD RTX TxC Tx+ Tx- TxE NC 6 25 24 23 22 21 20 19 4 3 2 1 28 27 26 NC 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Tx- NC CLK LPBK Rx+ 5 6 7 8 9 RSL XMT/RCV RxD RxC RxE CS2 CS1 DO+ DO- CLK 7 8 9 RSL JAB XMT CLS RCV RXD RxC RxE CS2 CS1 GND LPBK 10 GND 11 Rx+ 12 Rx- 13 NC 14 NC 15 DI+ 16 DI- 17 18 19 20 21 22 23 24 25 26 27 28 Rx- 10 NC 11 12 13 14 15 16 17 18 RPOL FD COL LTP VCC VCC CS0 CI+ CI- VCC VCC FD LTP AUI/TP RPOL COL ML2653 44-Pin TQFP (H44-10) JABDIS GND GND TxD RTX TxC Tx+ Tx- TxE NC NC NC NC CLK LPBK NC Rx+ Rx- NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 RSL JAB XMT CLS RCV RXD RxC RxE CS2 CS1 NC NC NC VCC VCC LTP AUI/TP NC RPOL COL 2 CS0 FD AUISEL CS0 ML2652/ML2653 ML2653 BLOCK DIAGRAM CS0 CS1 CS2 FD TxC TxE TxD ENABLE COL LPBK CONTROLLER INTERFACE COLLISION COLLISION DETECT RECEIVE LPF RECEIVER RSL VCC VCC GND GND DATA MANCHESTER ENCODER JABBER DETECT LINK PULSE XMT WAVEFORM GEN & LPF CURRENT DRIVEN XMT OUTPUT DRIVER RTX Tx+ Tx- Rx+ Rx- DATA MANCHESTER DECODER ENABLE RxC RxE RxD CLK LEDS OSC RPOL XMT/RCV LTP PIN DESCRIPTION NAME FUNCTION NAME FUNCTION VCC GND CLK Positive supply. +5V Ground. 0 volts. All inputs and outputs referenced to this point. Clock input. There must be either a 20 MHz crystal or a 20 MHz clock between this pin and GND. Transmit positive twisted pair output. This output is a current source that drives the twisted pair cable through a pulse transformer. Transmit negative twisted pair output. This output is a current source that drives the twisted pair cable through a pulse transformer. Receive positive twisted pair input. This input receives data from the twisted pair cable through a pulse transformer. Receive negative twisted pair input. This input receives data from the twisted pair cable through a pulse transformer. DI- CI+ CI- RTX AUI negative receive data input from optional external transceiver. AUI positive collision input from optional external transceiver. AUI negative collision input from optional external transceiver. Transmit current set. An external resistor between this pin and GND programs the absolute value of output current on Tx. Transmit clock output. Digital output which clocks the transmit data (TxD) into the device from the controller. Transmit data input. Digital input which contains transmit data from the controller. Transmit enable input. Digital input from the controller that indicates when the transmit data (TxD) is valid. Collision output Digital output to the controller which indicates when a collision condition is present. Receive clock output. Digital output which clocks receive data (RxD) from the device into the controller. Tx+ Tx- TxC Rx+ TxD TxE Rx- COL DO+ DO- DI+ AUI positive transmit output. AUI transmit data output to optional external transceiver. AUI negative transmit output. AUI transmit data output to optional external transceiver. AUI positive receive data input from optional external transceiver. RxC 3 ML2652/ML2653 PIN DESCRIPTION (Continued) NAME FUNCTION NAME FUNCTION RxD RxE Receive data output. Digital output which contains receive data sent to the controller. Receive data valid. Digital output to the controller that indicates when the receive data (RxD) is valid. Local loopback. Digital input from the controller which forces the device to loopback transmit data without sending it on the media. Full Duplex Enable. When enabled the 10BASE-T MAU loopback and collision detect are disabled. LPBK must be disabled when using this function. Controller selection input. Digital input which selects one of four standard controller timing interfaces. This pin has an internal pulldown resistor to GND. Controller select input. Digital input which selects one of four standard controller timing interfaces. This pin has an internal pulldown resistor to GND. Controller select input. Digital input which selects one of four standard controller timing interfaces. This pin has an internal pulldown resistor to GND. Receive squelch level select input. Pin has internal pullup resistor to VCC. RSL = High Receive squelch level = 10Base-T RSL = Low Receive squelch level = extended distance Transmit status output. Digital output which indicates data transmission on Tx+ and Tx-. Pin is open drain output with resistor pullup and is capable of driving an LED. XMT pin and RCV pin are the same pin for the ML2653. Receive status output. Digital output which indicates unsquelched data reception on Rx+ and Rx-. Pin is an open drain output with resistor pullup and is capable of driving an LED. CLS Collision status output. Digital output which indicates that collision condition has been detected. Pin is an open drain output with resistor pullup and is capable of driving an LED. Link test pass output/input. This pin consists of an open drain output transistor with a resistor pullup that serves both as a link test pass output and a link test disable input. When used as an output, this pin is capable of driving an LED. LTP = High, link test failed LTP = Low, link test pass LTP = GND, link test disabled LTP LPBK FD CS0 AUI/TP AUI/twisted pair interface select input. AUI/TP = High, AUI selected AUI/TP = Low, TP selected RPOL JAB This pin must be grounded at all times. Jabber detect output. Digital output which indicates that the jabber condition has been detected. Pin is an open drain output with resister pullup and is capable of driving a LED. JAB = High, normal JAB = Low, jabber detected CS1 CS2 RSL AUISEL AUI/TP port output status AUISEL = High, TP port selected AUISEL = Low, AUI port selected JABDIS Jabber disable input JABDIS = High, jabber disabled JABDIS = Low, normal operation NC No connect. Leave this pin open circuit. XMT RCV ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to GND. (Note 1) VCC supply voltage .................................................. +6.5V All inputs and outputs ....................... -0.3V to VCC + 0.3V Input current per pin ............................................. 25 mA Power dissipation .............................................. 0.75 Watt Storage temperature range ........................ -65C to 150C Junction Temperature .............................................. 150C Lead temperature (soldering, 10 sec) ....................... 260C Thermal Resistance (qJA) 28-Lead PLCC ................................................... 60C/W 44-Lead PLCC ................................................... 54C/W 44-Lead TQFP ................................................... 67C/W 4 ML2652/ML2653 ELECTRICAL CHARACTERISTICS (Continued) Unless otherwise specified TA = 0C to 70C, VCC = 5V +5%. Note 2 & 3. SYMBOL VIL PARAMETER Digital input low voltage CONDITIONS All except CLK CLK All except CLK CLK VIN=GND TxD, TxE, AUI/TP VIN=GND LPBK, CS2-0, LBDIS,JABDIS VIN=GND RSL VIN=GND LTP, RPOL, VIN=GND CLK VIN=VCC TxD, TxE, AUI/TP VIN=VCC LPBK, CS2-0, LBDIS, JABDIS VIN=VCC RSL VIN=VCC LTP, RPOL VIN=VCC CLK All except CLK CLK IOL=-2mA TxC, COL, RxC, RxD, RxE IOL=-10mA XMT, RCV, CLS, LTP, RPOL, JAB IOH=2mA TxC, COL, RxC, RxD, RxE IOL=10uA XMT, RCV, CLS, LTP, RPOL, JAB TX transmission No transmission Powerdown mode MIN TYP MAX .8 1.5 UNITS V V V V VIH Digital input high voltage 2.0 3.5 -5 -5 -50 -500 -300 1 50 1 1 250 IIL Digital input low current -10 -15 -25 -250 A A A A A A A A A A pF pF IIH Digital input high current 10 25 CIN Digital input capacitance 5 10 VOL Digital output low voltage .4 .6 V V VOH Digital output high voltage 4.0 2.4 140 105 2 V V mA mA mA ICC VCC supply current TOV Tx differential output voltage Tx harmonic distortion Tx common mode output voltage Tx common mode rejection Tx differential output voltage during idle Tx output current accuracy Tx output resistance Tx output capacitance RTX = 10K TxD=all ones 2.2 -27 2.5 2.8 Vp dB THD TCM 50 VCM=15vp, 10.1 MHz sine 100 mVp mVp TCMR TOVI 50 RTX=10K 50 1 10 mVp mA Mohm pF TOIA TRO TCO 5 ML2652/ML2653 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL RRI RCI RSON PARAMETER Receive input resistance Receive input capacitance Receive squelch on level (Differential zero to peak voltage) Receive squelch off level (Differental zero to peak voltage) DO differential output voltage DO differential output voltage during idle DOdifferential output voltage return to 0 undershoot RSL=1 RSL=0 CONDITIONS MIN 2.5K TYP 10K 10 MAX UNITS ohms pF 275 150 520 325 mVp mVp RSOF RSL=1 RSL=0 150 100 325 225 mVp mVp DOV 550 1170 mV DOVI 40 mV DOUS -100 mV DOCMA DO common mode AC output voltage DOCMA DO common mode DC output voltage DIRI DICI DIBV DISON t1 t2 t3 t4 t5 t6 t7 t8 DI/CI input resistance DI/CI input capacitance DI/CI input bias voltage DI/CI squelch on level TxC on time TxC off time TxC period TxE setup time TxE hold time TxD setup time TxD hold time Transmit propagation delay Tx DO 25 0 25 0 60 DI/CI floating -175 45 45 100 2.5K 40 mV VCC *.5 10K 10 VCC *.5 -325 55 55 V ohms pF V mVp ns ns ns ns ns ns ns 200 200 ns ns 6 ML2652/ML2653 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL t9 PARAMETER Start of Idle Pulse Width SOI pulse width to within 40mV of final value Transmit output jitter Tx DO Tx DO Tx DO CONDITIONS MIN TYP MAX UNITS 200 350 4500 8000 8.0 .5 ns ns ns ns ns t10 t11 t12 Transmit output rise and fall time TxE to XMT assert XMT blinker pulse period XMT duty cycle Start of receive packet to RxE assert Start of receive packet to RxC active RxC on time RxC off time RxD valid before RxC RxD valid after RxC RxE assert to RCV assert RCV blinker pulse period RCV duty cycle Receive input jitter Tx , 10-90% 5 250 95 45 115 55 600 200 1600 1300 45 45 45 35 250 95 45 115 55 12 18 160 160 30 20 100 60 45 200 900 55 ns ms ms % ns ns ns ns ns ns ns ns ms ms % ns ns ns ns ns ns ns t13 t14 t15 t20 Rx DI Rx+ DI+ t21 t22 t23 t24 t25 t26 t27 t28 t29 Preamble Data Tx DI t30 Receive propagation delay t31 t32 t33 RxC to RxE assert RxC to RxE deassert RxE deassert to RxC switchover 7 ML2652/ML2653 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL t34 PARAMETER Minimum SOI pulse width required for receive detection Jabber activation delayTxE assert to Tx disable Tx disable to JAB assert Jabber reset time - TxE deassert to JAB deassert Tx disable to COL assert Tx disable to CLS assert JAB deassert to COL deassert JAB deassert to CLS deassert Transmit link pulse period Minimum link pulse period required for receive detection Maximum link pulse period required for receive detection Receive link pulse no detect to LTP deassert Receive link pulse detect to LTP assert AUI/TP to AUISEL delay TxE deassert to COL assert COL pulse Width Start of RCV packet during transmission to COL assert Start of RCV packet during transmission to CLS assert End of RCV packet during transmission to COL deassert CLS blinker pulse period CLS duty cycle Rx Tx DI CONDITIONS MIN 180 180 20 TYP MAX UNITS ns ns t40 150 ms t41 t42 200 250 750 ms ms t43 t44 t45 t46 t51 t52 50 50 50 50 8 2 24 7 ns ns ns ns ms ms t52 25 150 ms t53 50 150 ms t54 2 Link Pulse t55 t60 t61 t70 200 .9 .9 1.0 1.0 1.1 1.1 500 ns s s ns t71 Rx 500 ns t72 Rx 300 ns t73 t74 95 45 115 55 ms % 8 ML2652/ML2653 ELECTRICAL CHARACTERISTICS (Continued) SYMBOL t75 PARAMETER Transmission start during reception to COL assert Transmission start during reception to CLS assert CI period CI duty cycle First valid negative CI data transition to COL assert First valid negative CI data transition to CLS assert Last CI positive data transition to COL deassert External clock input jitter Tx CONDITIONS MIN TYP MAX 300 UNITS ns t76 Tx 250 ns t77 t78 t79 80 40 120 60 100 ns % ns t80 100 ns t81 160 250 ns t82 Note 1: Note 2: Note 3: 50 ps Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Low Duty cycle pulse testing is performed at TA. 9 ML2652/ML2653 TIMING DIAGRAMS (Continued) TxC TxE TxD (NRZ) 1 1 1 1 0 0 0 0 1 0 1 1 COL1 SQE TEST MANCH. DATA XMT TWISTED PAIR 1 1 1 1 0 0 0 0 1 0 1 0 1 LINK PULSE 1 1 1 0 0 0 0 1 0 1 0 LINK PULSE LINK PULSE SOI PULSE Figure 1. Transmit System Timing RCV TWISTED PAIR RxC 1 0 1 1 1 1 0 0 0 0 1 0 1 0 RxE RxD (NRZ) 1 1 1 1 0 0 0 0 1 0 1 0 Figure 2. Receive Timing 10 ML2652/ML2653 TIMING DIAGRAMS (Continued) t1 TxC t4 TxE t7 t6 TxD B0 B1 t8 Tx t13 XMT B2 B3 t5 t2 t3 t9 B0 B0 B1 B1 B2 B2 B3 B3 t12 t11 t14 t15 40mV t10 Figure 3. Transmit Timing 1 Rx t20 RxE 0 1 0 1 0 1 0 1 0 t29 t21 RxC(1) t31 RxC(2) Tx Tx Tx Tx t22 Rx Rx t22 Rx t23 Rx t23 Rx Rx Rx Rx t24 Rx t25 1 0 Rx RxD t26 t28 RCV t27 1 0 NOTE: 1. RxC IS NOT CONTINUOUS DURING IDLE 2. RxC IS CONTINUOUS DURING IDLE Figure 4. Receive Timing - Start of Frame 11 ML2652/ML2653 TIMING DIAGRAMS (Continued) 0 Rx 0 1 SOI t34 RxE 5 EXTRA RxC FOR CS2 - 0 = 000 t32 RxC(1) Rx Rx Rx Rx Rx t33 t22 RxC(2) Rx t30 RxD 0 0 1 Rx Rx Rx Rx Tx Tx Tx Tx NOTE: 1. RxC IS NOT CONTINUOUS DURING IDLE -- 8 EXTRA CLOCKS ADDED FOR CS2 - 0 = 000 2. RxC IS CONTINUOUS DURING IDLE Figure 5. Receive Timing - End of Frame TxC TxE TxD t40 Tx t42 t43 COL t41 JAB t44 CLS t45 t46 Figure 6. Jabber Timing (ML2652 only.) 12 ML2652/ML2653 TIMING DIAGRAMS (Continued) TRANSMIT Tx RECEIVE Rx t52 LTP t53 t54 t51 AUI/TP INTERFACE SELECT t55 t55 AUISEL Figure 7. Link Pulse Timing TxC TxE TxD t60 COL t61 Figure 8. SQE Test Timing 13 ML2652/ML2653 TIMING DIAGRAMS (Continued) TxD Tx DATA MAY BE INVALID RxD Rx t70 COL t72 t71 CLS t73 t74 Figure 9. Collision Timing Reception During Transmission Rx TxE TxD Tx t75 COL t76 CLS t74 t82 t73 Figure 10. Collision Timing Transmission During Reception 14 ML2652/ML2653 TIMING DIAGRAMS (Continued) t78 CI t79 COL t80 CLS t73 t81 t77 t78 Figure 11. CI Collision APPLICATION CIRCUIT -- ML2652 +5V 0.1F +5V 0.1F +5V 200 1% +5V VCC TxC TxD TxE COL RxC RxD RxE FD LPBK CS0 CS1 CS2 JABDIS RSL AUI/TP XMT RCV CLS AUISEL LTP RPOL JAB VCC 200 1% Tx+ 2:1 Tx- Rx+ 98 1% Rx- ETHERNET CONTROLLER 1:1 RJ45 (SEE TABLE 1) SEEQ 8003 SEEQ 8005 NSC DP8390 AMD AM7990 INTEL 82586 +5V INTEL 82596 510 ML2652 DO+ 78 DO- CI+ 78 CI- DI+ 78 DI- AUI 6 +5V 5.1K 5.1K 510 CLK GND GND RTX 10K Figure 12 15 ML2652/ML2653 FUNCTIONAL DESCRIPTION GENERAL The ML2652 and ML2653 are composed of a transmitter section, receive section and some miscellaneous functions. The transmit section consists of the manchester encoder, AUI, jabber detect, link pulse generator, start of idle (SOI) pulse generator, waveform generator, and line driver. The purpose of the transmit section is to take data from the controller, encode it, and transmit it over either the AUI or twisted pair interface. In addition, the transmit section generates link pulses, start of idle pulses, and checks for jabber condition. The transmitter keeps the data jitter to a maximum of 8.0ns, and the maximum delay through the transmission section is less than 2 bits, or 200ns. The receive section consists of the manchester decoder, collision detect, AUI, receive LPF, receive comparators, receive squelch, automatic polarity correct, start of idle (SOI) detect, and link pulse detect. The purpose of the receive section is to take data from either the twisted pair cable or AUI, decode it, then send the data to the controller via the controller interface. In addition, the receive section detects and automatically corrects for reverse polarity, detects link pulses, detects start of idle pulses, and implements an intelligent receive squelch algorithm. The receive section can successfully lock onto an incoming data that contains 18ns of jitter in less than 1.6s. The miscellaneous functions are the controller interface, single pin crystal oscillator, AUI, loopback modes, test mode, and powerdown mode. The ML2653 has no AUI interface output. The following text describes each of these blocks and functions in more detail. Refer to the block diagram. TRANSMISSION The transmit data (NRZ) is first clocked into the device through the controller interface. The device can be digitally programmed to accommodate any one of four standard Ethernet controllers as described in Controller section. APPLICATION CIRCUIT -- ML2653 +5V 0.1F +5V 0.1F VCC TxC TxD TxE COL RxC RxD RxE FD LPBK CS0 CS1 CS2 +5V RSL 5.1K 510 510 RPOL XMT/RCV LTP VCC Tx+ +5V 200 1% +5V 200 1% 2:1 Tx- Rx+ 98 1% Rx- ETHERNET CONTROLLER 1:1 RJ45 (SEE TABLE 1) SEEQ 8003 SEEQ 8005 NSC DP8390 AMD AM7990 INTEL 82586 +5V INTEL 82596 ML2653 CLK GND GND RTX 10K Figure 13 16 ML2652/ML2653 FUNCTIONAL DESCRIPTION (Continued) RTX = K*Vb/Iout = 125*4v/50mA The manchester encoded data then goes to either the AUI or twisted pair interface. The selection of the appropriate interface is automatic. If the AUI is selected, the manchester encoded data is transmitted out differentially on the DO+ and DO- pins, and the twisted pair line driver is disabled. If the twisted pair interface is selected, the manchester encoded data is transmitted out differentially on Tx+ and Tx- pins, and the transmit AUI is disabled. Refer to the AUI section for details on how the AUI and automatic interface selection is accomplished. Assuming that the twisted pair interface is selected, the Manchester encoded data then goes to the transmit waveform generator. The transmit waveform generator takes the digital Manchester encoded data and generates a waveform. When this waveform is passed through the cable model in the 10BASE-T standard (figure 14-7 IEEE Std 802.3i-1990) it meets the voltage template (figure 14- 9 IEEE Std 802.3i-1990). The transmit waveform generator is composed of a 16 x 4 bit ROM, 4 bit DAC, 3rd order LPF, and clock generator. The DAC is used to synthesize a stair-step representation of a signal that will meet the required output template. The ROM stores the digital representation of the output signal and provides a digital input to the DAC. The ROM is addressed by a 16 phase clock generator that is locked to the transmit clock TxC. The high frequency content present in the output of the DAC is removed by a 3rd order continuous LPF which smooths the output. The transmit line driver takes the output of the waveform generator and converts this voltage to a differential output current on Tx+ and Tx- pins. When one transmit output (either Tx+ or Tx-) is sinking current, the other output is high impedance, and vice versa. In this way, a differential output voltage is developed by sinking this output current through two external 200 ohm terminating resistor and a 2:1 transformer as shown in Figure 12. Setting the external terminating resistors to 200 ohms as shown in Figure 12 will implement a 100 ohm terminating impedance when looking back through the transformer. If other terminating impedances are required (such as 150 ohm), the terminating resistor values can be adjusted accordingly as long as the output current stays within the minimum and maximum limits (30-70mA). The absolute value of the output current, and subsequently the output voltage level, is set by an external resistor between RTX and GND. If RTX = 10k ohms and Tx is terminated as shown in Figure 12, the output level is 2.5V which meets 802.3i-1990 differential output voltage requirements. If a different output current/voltage level is desired, the level can be changed by changing the value of RTX according to the following formula: RTX = 10kW When data is being transmitted (and there is no collision or link pulse fail condition), the transmit data is looped back to the receive path, and the Manchester decoder will lock onto the transmit data stream. After data transmission is completed, the transmitter sends a start of idle (SOI) pulse to signal the end of a packet. During the idle period, Tx+ and Tx- are held low. Occasionally, link pulses are transmitted during the idle period. The XMT pin is an output that indicates transmit activity. The pin consists of an open drain output with an internal pull-up resistor and can drive an LED from VCC or another digital input. In order to make an LED visible, XMT has an internal blinker circuit that generates a 100ms blink (50ms high, 50ms low) that is triggered when a trans-mission starts. At the completion of the 100ms blink period, if a transmission is in progress, another 100ms blink is generated. Then the NRZ data is encoded by the manchester encoder as shown in transmit timing diagram in Figure 1. RECEPTION The twisted pair receive data is typically transformer coupled and terminated with an external resistor as shown in Figure 12. The output of the transformer is then applied to the device input pins Rx+ and Rx-. The input is differential, and the common mode input voltage is biased to VCC/2 by two internal 10K bias resistors from Rx+, Rx- to VCC/2. The Rx+ and Rx- inputs then go to the receive filter. The receive filter is a continuous 3rd order LPF and has the following characteristics: 1. 3 dB cut-off frequency 2. Insertion Loss (5-10 MHz) 3. 30 MHz attenuation 15 MHz - 1.0 dB 17.5 dB min. The output of the filter goes to the receive comparators. There are two receive comparators inside the chip, threshold and zero crossing. The threshold comparator determines if the receive data is valid by checking the input signal level against a predetermined positive and negative squelch level. Once the threshold comparator determines that valid data is being received, the zero crossing comparator senses zero crossings to determine data transitions. Both comparators are fast enough to respond to 12ns pulse widths with minimum squelch overdrive. 17 ML2652/ML2653 FUNCTIONAL DESCRIPTION (Continued) Clock and data recovery is accomplished by a digital PLL which can lock on the incoming bit stream in less than 1.6s. The clock (RxC) and NRZ data (RxD) are then output to the external world via the controller interface. The receive squelch circuit determines when data on incoming Rx+, Rx- is valid. The receive squelch is considered "on" when the data is deemed to be invalid, and the receive squelch is considered "off" when data is determined to be valid. The input signal must meet the following criteria in order to turn receive squelch off and be recognized as valid data: 1. The input signal must exceed the receive squelch on level. When this occurs, a 400ns squelch interval timer is started. 2. During the 400ns squelch interval, the input signal must go from one squelch threshold to the opposite polarity squelch threshold in less than 127ns. 3. During the 400ns squelch interval, the input signal has to make less than 9 squelch threshold to opposite polarity squelch threshold crossings. When the receive squelch is turned off, the receive squelch off level is reduced to 2/3 of receive squelch on level. The receive squelch will be turned back on if either the incoming data peaks go below the receive squelch off level for 400ns or the start of idle (SOI) pulse is detected. The receive squelch on level can be digitally programmed for one of two possible levels by using the RSL pin. When RSL = 1, the squelch on level complies with the IEEE 802.3i-1990 specification. When RSL = 0, the receive squelch on level is lowered in order to accommodate greater receive attenuation and consequently longer twisted pair cable lengths. The receive squelch on level can be programmed as follows: SOI A start of idle (SOI) pulse is sent at the end of transmission in order to signal to all receivers that transmission has ended and the idle period begins. Thus, the transmit section has an SOI generator and the receive section has an SOI detector. The transmit SOI pulse generator inserts an SOI pulse at the end of each transmission. The SOI pulse is typically a 250ns positive pulse inserted after the last positive data transition. Depending on the data pattern, the positive data transition could occur either in the middle or at the end of the last bit cell. So the actual width of the transmitted SOI pulse can vary from 250-300ns, typically. The receive SOI detector senses the SOI pulse using the zero crossing comparator. When the SOI pulse is detected, the receiver signals to the controller that receive data is no longer valid and turns the receive squelch on. LINK PULSE During the idle period, link pulses are sent by the transmitter and detected by the receiver so that the integrity of the twisted pair link can be continuously monitored. Thus, the transmit section has a link pulse generator, and the receiver has a link pulse detector. The transmit link pulse generator transmits a 100ns wide positive pulse (Tx+ high, Tx- low) every 16 8ms. IEEE 802.3i-1990 Section 14 requires the link pulse to be shaped to meet a template when passed or not passed through the twisted pair line model. The transmit waveform generator takes the link pulse and generates the waveform on TX when passed or not passed through the twisted pair line model. The receiver monitors the receive input to determine if the link pulses are present. When the device is in the link pulse pass state, normal packet transmission and reception can occur. All link pulses less than 2-7ms apart are ignored while in the link pass state. If no link pulses or receive packets are detected for a period of 50-150ms, the device goes into the link pulse fail state. When the device is in the link pulse fail state, reception is inhibited and the transmitter is placed in the idle state (no data transmission but link pulses are still transmitted). In order for the device to exit the link pulse fail state, one complete packet or 4 consecutive link pulses must be detected, and transmit and receive must be idle. Consecutive link pulses are defined as pulses that occur within 25-150ms of each other. If the link pulses occur RSL 1 0 RECEIVE SQUELCH ON LEVEL Application Min Typ 10BASE-T Long Distance 300 200 Max 585mV 390mV The RCV pin is an output that indicates receive activity. The pin consists of an open drain output with an internal pull-up resistor and can drive an LED from VCC or another digital input. In order to make an LED visible, RCV has an internal blinker circuit that generates a 100ms blink (50ms high, 50ms low) that is triggered when reception starts. At the completion of the 100ms blink period, if reception is in progress, another 100ms blink is generated. The manchester decoder receives data from either the twisted pair interface (as described above) or the AUI (described in AUI section). The manchester decoder is responsible for recovering clock and data from the incoming receive bit stream. 18 ML2652/ML2653 FUNCTIONAL DESCRIPTION (Continued) pull-up resistor and can drive an LED from VCC or another digital input. In order to make an LED visible, CLS has an internal blinker circuit that generates a 100ms blink (50ms high, 50ms low) that is triggered when a collision starts. At the completion of the 100ms blink period, if collision is in progress, another 100ms blink is generated. 2-7ms apart in the link fail state, the device ignores the link pulses and resets the number of consecutive link pulses to zero. After the link pulse fail state is exited, transmission and reception can be resumed. Link pulse status is indicated by the LTP pin. LTP is a dual function input/output pin that acts both as an active low link test pass output and a link test disable input. The pin consists of an open drain output with an internal pull-up resistor. If the pin is tied to GND, the pin acts as an input and the link test function is disabled. If the pin is not tied to GND, the pin acts as an active low link test pass output and can drive an LED from VCC or another digital output. Thus, the LED is lit when the link test is passing. SQE TEST When the twisted pair interface is used, the device tests the collision circuitry at the end of each transmission by sending a 1s collision pulse over the COL pin. This is known as SQE (signal quality error) test and is shown in the transmit timing diagram in Figure 1. The SQE test is disabled if the device is in jabber detect state or link pulse fail condition. When AUI is used (ML2652), the SQE test pulse is generated by an external MAU and the external MAU sends the SQE test pulse to the ML2652 via the collision inputs , CI+ and CI-. The ML2652 then relays the collision signal to the controller via the COL and CLS output pins. JABBER The transmit section contains a jabber detect circuit. Jabber is a fault condition characterized by a babbling transmitter. The ML2652 and ML2653 detect jabber when a transmission packet exceeds 20-150ms in length. If jabber detect occurs, the transmit output is disabled, the collision signal COL is sent over the controller interface, and the JAB pin is pulled low. The device remains in the jabber detect state until there is at least 250-750ms of continuous non-transmission. Note that link pulses continue to be transmitted even when the device is in the jabber condition. The jabber detection circuitry can be disabled (only on the ML2652) with the JABDIS pin for testing and diagnostic purposes. Disabling jabber means that a jabber condition is never recognized, even when it occurs. JABDIS is an active high jabber disable input and has an internal pulldown resistor to GND. RECEIVE POLARITY DETECT AND AUTO CORRECTION The ML2652 and ML2653 contain an auto-polarity circuit that detects the polarity of the receive twisted pair leads, Rx+ and RX-and internally reverses the leads if their polarity is incorrect. When the device is powered up, it is assumed that the polarity is correct and no polarity correction occurs. Then receive polarity is continuously monitored by checking the polarity of the SOI and link pulses since they are always positive pulses. If either 2 consecutive SOI or 4 consecutive link pulses have incorrect RX polarity, then the auto-polarity circuit internally reverses the Rx+ and Rx- connections. COLLISION Collision occurs whenever the DTE card is transmitting and receiving data simultaneously. However, the collision circuit on the ML2652 operates differently depending on whether twisted pair interface or AUI is being used. When the twisted pair interface is used, collision occurs whenever the device is transmitting and receiving data simultaneously, that is when both RxE and TxE are active. The collision state is indicated by COL and CLS pins. COL is used to signal collision to the controller. CLS is an active low open drain output. CLS is activated during Jabber, but not during SQE test while COL is activated during both. When the AUI is used (ML2652 only), collision is no longer detected from simultaneous transmission and reception, but the collision state is determined when a collision signal is present on the AUI collision inputs, CI+ and CI-. A 10 MHz square wave has to be applied to this input in order for the device to signal the collision state on COL and CLS. The CLS pin is an output that indicates collision activity. The pin consists of an open drain output with an internal AUI (APPLIES ONLY TO ML2652) The ML2652 can be used with an external MAU via the Attachment Unit Interface (AUI). When the AUI is used, the internal MAU functions and twisted pair interface are disabled, and the device only uses the manchester encoder and decoder functions, as shown in the block diagram. The AUI consists of three differential signal pairs: DI, DO, and CI. The function of each pair is described below. The DO+ and DO- are differential outputs to the external MAU which contain the transmit data output from the Manchester encoder. The DO+ and DO- output drivers are capable of driving 50 meters of 78 ohm cable with less than 5ns rise and fall time and less than 0.5ns of jitter. In addition, at the end of transmission, the AUI output driver inserts a 200ns minimum pulse and meets the turnoff and idle characteristics specified in IEEE 802.3-1988. An external 78 ohm resistor across DO+ and DO- is required as shown in Figure 12 to develop the proper output levels from the internal current sources. The DO+ and DO- 19 ML2652/ML2653 FUNCTIONAL DESCRIPTION (Continued) The AUISEL pin is a digital status output that indicates which interface has been selected for data transfer, either twisted pair or AUI. The pin consists of an open drain output with an internal pull-up resistor and can drive an LED from VCC or another digital input. AUISEL = High indicates that the twisted pair interface has been selected. AUISEL = Low indicates that the AUI interface has been selected. The ML2652 has the capability to automatically select between the twisted pair interface and AUI. This automatic interface selection is accomplished by tying the LTP output pin to the AUI/TP input pin. When these two pins are connected together, if valid link pulses are detected, it is assumed that the twisted pair interface is being used. This causes LTP output to go low, thus forcing AUI/TP low, and thus enabling the twisted pair interface. If no valid link pulses are detected, it is assumed that the twisted pair interface is not being used, thus causing LTP to go high, thus forcing AUI/TP high, thus enabling the AUI interface. If valid link pulses reappear, the device will automatically disable the AUI and enable the twisted pair interface. The algorithm for determining valid link pulses is described in the Link Pulse section. outputs can be coupled to an external MAU with either capacitors or a transformer. The ML2652 meets all AUI transmitter specifications outlined in IEEE 802.3-1988 Section 7. DI+ and DI- are inputs from the external MAU which contain the receive data that goes to the manchester decoder. The DI+ and DI- inputs contain an AUI DI squelch circuit which determines when incoming data on DI+ and DI- is valid. The DI squelch is considered "on" when the data is deemed to be invalid, and the DI squelch is considered "off" when data is determined to be valid. The input signal on DI+ and DI- must meet the following criteria in order to turn receive squelch off and be recognized as valid data: 1. The input signal must exceed the negative AUI DI squelch on level. 2. The input signal must exceed the negative AUI DI squelch on level for more than 20ns. When the DI squelch is turned off, the DI squelch off level is reduced to 2/3 of the DI squelch on level. The DI squelch circuit will be turned back on if the idle period is detected by no DI squelch level transitions for more than 180ns. An external 78 ohm termination resistor is needed across DI+ and DI- as shown in Figure 12. The DI+ and DI- inputs can be coupled from an external MAU into the ML2652 with either capacitors or a transformer. The ML2652 meets all AUI receiver specifications outlined in IEEE 802.3-1988 Section 7. CI+ and CI- are inputs from the external MAU which contain the 10 MHz 15% collision signal as defined in IEEE 802.3-1988 Section 7. The CI+ and CI- inputs contain the same squelch circuit used on the DI inputs described in previous paragraphs in this section. An external 78 ohm termination resistor is needed across CI+ and CI- as shown in Figure 12. The CI+ and CI- inputs can be coupled from an external MAU into the ML2652 with either capacitors (shown in Figure 12) or a transformer. The ML2652 meets all AUI receiver specifications outlined in IEEE 802.3-1988 Section 7. The ML2652 contains an AUI/TP select input pin which controls whether the AUI or twisted pair interface is to be used for data transmission and reception. When AUI/ Twisted Pair Switching = High, the AUI is used for data transmission and reception. When AUI/Twisted Pair Switching = Low, the twisted pair interface is used for data transmission and reception. LOOPBACK LPBK provides a loopback through the manchester encoder/decoder, but not through the on-chip 10BASE-T MAU. No data will go out on either the AUI port or the twisted pair port in this mode. This same function is found on many discrete manchester encoder/decoders. IEEE 802.3 MAUs normally loop the transmit data (DO+) when transmitting with no collisions. When using an external transceiver through the ML2652's AUI port, the controller can first check the local loopback by setting LPBK. If it passes this test it can then check the AUI cable and external MAU by doing the normal MAU loopback. FULL DUPLEX OPERATION The ML2652 and ML2653 are capable of operating in the full duplex mode which transmits and receives data simultaneously. In the full duplex mode the collision circuitry is disabled just as it is in the loopback mode. To achieve full duplex operation the full duplex pin FD is enabled and the loopback pin LPBK must be disabled. Both of these conditions must be present to operate in the full duplex mode. CONTROLLER INTERFACE The ML2652 and ML2653 has a flexible and programmable digital interface which enables it to directly interface to Ethernet controllers manufactured by Intel, AMD, National and Seeq. 20 ML2652/ML2653 FUNCTIONAL DESCRIPTION (Continued) connecting an external crystal or an external clock between the CLK and GND pins. If an external clock is used, it must have a frequency of 20 MHz 0.01% and have high and low levels of 3.5 and 1.5 volts. If a crystal is used, the crystal should be placed physically as close as possible to the CLK and GND pins, especially CLK. No other external capacitors or components are required. The crystal should have the following characteristics: 1. Parallel resonant type 2. Frequency: 20 MHz 3. Tolerance: 0.005% @ 25C 4. Less than 0.005% frequency drift across temperature. 5. Maximum equiv. series resistance: 15 ohms @ 1-200W 30 ohms @ 0.01-1W 6. Typical load capacitance: 20pF The ML2652 requires an accurate 20 MHz reference for internal clock generation. This can be achieved by 7. Maximum case capacitance: 5pF The controller interface consists of seven pins. TxC, TxD, and TxE are the transmit clock output, transmit data input, and transmit data enable input, respectively. RxC, RxD, and RxE are the receive clock output, receive data output, and receive data enable output, respectively. COL is the collision detect output. All the standard Ethernet controllers use a similar controller interface but differ in the polarity of COL, LPBK, TxE and RxE, and in what edge of TxC and RxC that clocks in the data. They also differ on whether the RxC clock needs to be continuous or not during idle, and on the polarity of RxD during idle. In order to accommodate the different controller interface definitions, the controller select pins, CS2-0, modify these signals according to Table 1. POWERDOWN The device can be placed in the power down mode with the controller select pins CS2-0 as described in Table 1. When in powerdown mode, the current consumption is reduced to less than ZmA and all device functions are disabled. CRYSTAL OSCILLATOR Table 1. Controller Select Pin Definitions CS2-0 000 001 010 TxC r f r TxE h l h RxC r f r RxE h l h COL h l h LPBK h l h Idl RxC m n n Idl RxD l hi hi NSC Intel Controller DP8390 82586/96 AMD AM7990 Motorola* Seeq -- -- -- PDN mode 8003/5 011 100 101 110 111 f -- -- -- -- h -- -- -- -- r -- -- -- -- h = active high l = active low h -- -- -- -- h -- -- -- -- l -- -- -- -- c -- -- -- -- lo -- -- -- -- r = rising edge clocks data f = falling edge clocks data c = RxC required continuously n = RxC only during RxD transmission m = RxC only during RxD transmission + 5 extra RxC cycles * AMD mode is also recommended for all Motorola's QUICC, Power QUICC or simlar Communications Controllrs (MPC850, MPC860m ....). These controllers should be 5V or 3.3 V devices with 5V-friendly I/O pins 21 ML2652/ML2653 PHYSICAL DIMENSIONS inches (millimeters) Package: Q44 44-Pin PLCC 0.685 - 0.695 (17.40 - 17.65) 0.650 - 0.656 (16.51 - 16.66) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.042 - 0.048 (1.07 - 1.22) 12 PIN 1 ID 0.650 - 0.656 0.685 - 0.695 (16.51 - 16.66) (17.40 - 17.65) 0.500 BSC (12.70 BSC) 0.590 - 0.630 (14.99 - 16.00) 34 23 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.112 (2.54 - 2.84) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE Package: Q28 28-Pin PLCC 0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 0.042 - 0.048 (1.07 - 1.22) PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92) 15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.099 - 0.110 (2.51 - 2.79) 0.013 - 0.021 (0.33 - 0.53) SEATING PLANE 22 ML2652/ML2653 PHYSICAL DIMENSIONS inches (millimeters) Package: H44-10 44-Pin (10 x 10 x 1mm) TQFP 0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 34 1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC) 0 - 8 0.003 - 0.008 (0.09 - 0.20) 23 12 0.032 BSC (0.80 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05) 0.018 - 0.030 (0.45 - 0.75) SEATING PLANE ORDERING INFORMATION PART NUMBER ML2652CQ ML2653CQ ML2653CH TEMPERATURE RANGE 0C to 70C 0C to 70C 0C to 70C PACKAGE 44-Pin PLCC (Q44) 28-Pin PLCC (Q28) 44-Pin TQFP (H44-10) (c) Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. DS2652_53-01 Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 www.microlinear.com 12/9/98 Printed in U.S.A. 23 |
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